Also known as:

• DEC 21554

Description:

The PCIIntel 21554 is a PCI peripheral device designed for embedded and intelligent I/O applications. It acts as a nontransparent PCI-to-PCI bridge with a 64-bit primary and secondary interface, supporting 33-MHz capability. The 21554 allows a local processor to independently configure and control the local subsystem, functioning as an intelligent I/O processor (IOP) in an I2O-capable system.

Key Features:

• Architecture independent, compatible with any host and local processors supporting a PCI bus.
• Bridges between two processor domains: the primary interface (host domain) and the secondary interface (local domain).
• Supports independent primary and secondary PCI clocks, address spaces, and address translation.
• Presents the subsystem as a single device to the host processor using a Type 0 configuration header, simplifying driver loading and local processor initialization.
• Translates addresses between the primary and secondary domains, hiding subsystem resources from the host and resolving resource conflicts.
• Operates at 3.3V with 5.0V tolerant I/O, allowing use in both 5V and 3V slots.

Additional Features:

• Full compliance with PCI Local Bus Specification Revision 2.1.
• Supports vital product data (VPD) and Compact PCI Distributed Hot-Swap.
• Supports asynchronous or synchronous primary and secondary interface clocks.
• Provides queuing of multiple transactions, read and write buffering, and delayed transaction entries.
• Features configuration registers, transaction forwarding, and intelligent I/O support with an I2O message unit.
• Includes ROM interfaces for parallel flash and serial ROM.
• Supports secondary bus arbiter, secondary bus clock output, and IEEE Standard 1149.1 boundary-scan JTAG interface.

Please refer to the user manual for detailed information and configuration options for the PCIIntel 21554 PCI-to-PCI Bridge for Embedded Applications.