UMC UM82C230 (286 MORTAR)

Description:

The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic alternative for building a reliable IBM PC/AT compatible system. A commercial 12MHZ/O wait state, 4MByte main memory system and math-coprocessor can be easily built by using 3 VLSIs, 8 logic components plus memory and processor.

Features:

  • Fully PC/AT-Compatible for 1OMHz and 12MHz systems.
  • Guaranteed zero wait state for 80ns DRAMs at 12MHz and one wait state for 120ns DRAMs at 125MHz.
  • Supports up to 4MB local memory on board.
  • Remaps 384KB of top of system local memory space.
  • Supports 1M/256K SIM module.
  • Supports 12MHz operation with one wait state for 200ns EPROM.
  • Commercially available BIOS (Phoenix/Award/AMI) applicable.
  • Easy design system board, three VLSI chips and eight TTLs configure all the logic.
  • Landmark speed=15.9MHz operating at 12MHz, 165MHz operating at 12.5MHz.

The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory Controller, the UM82C232 Data/Address Buffer and the UM82C206 Integrated Peripherals Controller (IPC).

As shown in the System Block Diagram, there are three data buses: local data bus, AT data bus and peripheral data (XD) bus. The local DRAM, EPROM and Numerical Processor are located on the local data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus. The AT data bus was driven by the UM82C232 directly which conveys the data to/from the AT Channel Adaptors.

The address bus architecture is also very simple; local CPU address bus, local DRAM address bus (MA), peripheral address bus (XA) and AT address bus. The local address bus is shared between CPU, UM82C231 and UM82C206. The MA bus is used by the local DRAM only. Most of the system board devices are attached to the XA bus, like UM82C232, UM82C206, ROMs and 8042. Some AT address lines are driven by the UM82C231 or UM82C232 directly; the others are buffered.

Last updated 2019-04-30T00:00:00Z
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