Description:

The UM82C231 provides synchronization and control signals for all buses. The UM82C231 also distinguishes if the current cycle is local memory cycle. Upon detecting that it is a local DRAM cycle, no AT control signals are sent out to the AT channel. The UM82C231 is based on the memory configurations to complete the current cycle with fastest response. If the cycle is AT cycle, the UM82C231 sends out the control signals sequentially which are then used by the adaptors or system board devices to receive the write data or to send the fetched data. Then, depending on the status signals sent back by the adaptors or system board devices, the UM82C231 determines which kind of AT cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert, or 0 wait state cycle.