Overview:

The Intel 82350 EISA chip set is the industry's first 100% EISA/ISA compatible chip set. The 82350 EISA chip set supports the 33 MHz and 25 MHz 386 CPU or i486 CPU, 82385 Cache Controller, and optional 80387 numerics coprocessor. The EISA chip set includes three chips:

82352 EISA Bus Buffers (EBB) (Optional)
82357 Integrated System Peripheral (ISP)
82358 EISA Bus Controller (EBC)

The ISP performs the DMA functions of the system and is fully compatible with ISA functions. It integrates seven 32-bit DMA channels, five 16-bit timer/counters, two eight channel interrupt controllers, and provides for multiple NMI control and generation. It provides refresh address generation and keeps track of pending refresh requests when the bus is unavailable. The ISP supports multiple EISA bus masters while offering intelligent system arbiter services which grant the bus on a rotational basis.

The EBC is the EISA "engine". It is an intelligent bus controller that controls 8, 16 and 32-bit bus masters and slaves. It provides the state machine interface to Host, ISA and EISA busses and other IC's in the chip set. It offers a simple interface to the 386/i486 CPU and EISA bus. The EBC services as a bridge between the EISA and ISA devices. Data bus size mismatches are handled automatically by the EBC (including byte assembly and disassembly). It also guarantees cache operation on the Host, EISA, and ISA busses.

Configurations:

82352 EISA Bus Buffers (EBB) (Optional up to 3x)
82357 Integrated System Peripheral (ISP)
82358 EISA Bus Controller (EBC)

The short form (Sep '92) datasheet we have in the downloads section makes reference to the 82358DT and 82352DT. This is a later datasheet written after the introduction of the 350DT chipset.