Description:

82357 Integrated System Peripheral (ISP)

The 82357 is a multi-function support peripheral that is designed to work in conjunction with the 82358 or 82358DT EISA Bus Controller to provide most of the system functions necessary in EISA specific applications.

The 82357 is comprised of several computer system functions that are typically found in separate LSI and VLSI components. These include: a high performance seven-channel programmable DMA Controller; an arbitration scheme that allows efficient bus sharing among multiple EISA masters, the host CPU, and DMA devices; a 16 level programmable interrupt controller which provides level-or-edge triggered interrupt capability on a channel-by-channel basis; non-maskable interrupt logic for multiple NMI control and generation; refresh address generation and control; and five counter/timers which provide a system timer interrupt, diskette time-out, DRAM refresh requests, and other system timing operations.

The DMA controller on the 82357 provides the timing control signals necessary to support a DMA data transfer rate of 33 Mbytes/sec. The DMA controller includes full function 32-bit addressability with control signal support for the transfer of data between devices of different data path widths using a single channel. Each channel functions independently in several modes.

Features:

• Provides Enhanced DMA Functions
  • ISA/EISA DMA Compatible Cycles
  • All Transfers are Fly-By Transfers
  • 32-Bit Addressability
  • Seven Independently Programmable Channels
  • Provides Timing Control for 8-, 16-, and 32-Bit DMA Data Transfers
  • Provides Timing Control for Compatible, Type "A", Type "B", and Type "C" (Burst) Cycle Types
  • 33 Mbytes/sec Maximum Data Transfer Rate
  • Provides Refresh Address Generation
  • Supports Data Communication Devices and Other Devices That Work from a Ring Buffer in Memory
  • Incorporates the Functionality of Two 82C37A DMA Controllers
• Provides High Performance Arbitration
  • For CPU, EISA/ISA Bus Masters, DMA Channels, and Refresh
• Incorporates the Functionality of Two 82C59A Interrupt Controllers
  • 14 Independently Programmable Channels for Level-or-Edge Triggered Interrupts
• Five Programmable 16-Bit Counter/Timers
  • Generates Refresh Request Signal
  • System Timer Interrupt
  • Speaker Tone Output
  • Fail-Safe Timer
  • Periodic CPU Speed Control
  • 82C54 Programmable Interval Timer Compatible
• Provides Logic for Generation/Control of Non-Maskable Interrupts
  • Parity Errors for System and Expansion Board Memory
  • 8 us and 32 us Bus Timeout
  • Immediate NMI Interrupt via Software Control
  • Fail-Safe Timer
• 132-Pin PQFP Package