Description:

VL82C3216 Bus Expanding Controller (BANC) Cache with Write Buffer

The VL82C3216 Bus Expanding Controller (BANC) Cache with Write Buffer is specifically designed to provide a high-performance, low-cost solution for interfacing 386SX PC/AT-compatible chip sets to 386DX, Am386DXL, AM386DXLV, 486DX, 486SX, or compatible processors. The designs may be entirely new systems or upgrades to existing ones. Power management features also make this device ideal for laptop computers or other battery operated systems. The performance is achieved through the use of a write buffer structure, an external second level cache, prediction algorithms, and maximizing the internal first level cache of the i486, if used.

The high level of integration is entered on the VL82C3216. It controls all functions between the host processor bus and the 386SX local bus. in addition the the write buffer and second- and first-level cache controls, the VL82C3216 contains prediction and burst mode algorithms that take full advantage of the page mode design of existing 386SX system architecture. Through the use of pipelined page mode accesses to system memory, the VL82C3216 bursts data to and from memory at rates of up to 25 MB per second. This provides 32-bit memory performance at 16-bit memory costs.

Features:

• High-performance 386DX, 486SX or 486DX interface
• Write buffer - 64 byte (16 DWord)
• External second-level cache - 128 KB
• i486 internal cache control
• BIOS control of second-level cache
• 386SX local bus emulation
• 386SX local bus address pipelining with four word FIFO
• 32-16 bit cycle type translation
• Auto peek cycle operations for both first and second-level cache
• i486 BIOS initialize
• 40 MHz max CPU freq @ 5.0V
• 33 MHZ max SX freq @ 5.0V
• 25 MHz max CPU and SX freq @ 3.3V
• Power management plus support for AMD's system Management Mode (SMM)
• 0.8-micron CMOS technology
• 160-lead metric quad flat pack (MQFP)