UM82C480 386/486 PC Chip Set

Q: My motherboard is listed as having this chipset but I have a 391 part instead of 481 part. Why is this chipset linked to the board?

A: Sometimes a motherboard has the chips swapped. The manufacture built the same board but by putting the 391 part on instead, it only supports 386 CPUs. Usually we link directly to the UM82C390 40MHz 386 PC Chip Set, however if you are here it is because the motherboard also comes in this configuration.

Documented parts

• UM82C481
• UM82C482
• 82C206

The UM82C481, Integrated Memory Controller (IMC), is part of UMC's high performance 80386/ 80486 PC/AT chip set. It contains sophisticated direct-mapped cache controller with write back operation, and fast page mode DRAM controller. Incorporated with UM82C482, Integrated System Controller (SC), and UM82C206, Integrated Peripheral Controller IPC), IMC provides main memory management function for the PC/AT computer system.

Features:

• Built-in cache controller:
• Direct-mapped organization with write-back operation
• Cache controller can be enabled/disabled
• 0 wait state for cache read/write hit if CPU is 80386
• Programmable 80486 read hit wait state for burst mode
• Programmable 80486 write hit wait state
• Programmable cache line size (4/8/16 bytes) if CPU is 80386
• Flexible cache size: 32/64/128/256/512/1024 KB
• Support interleaved cache RAM for high-speed CPU
• Hidden DRAM refresh to boost system performance
• Support Local Bus Access cycles
• Support three independent non-cacheable regions
• Video and System BIOS can be cacheable/non-cacheable, write-protected shadow RAM (16 KB resolution for C and D segments)
• Support fast GATE A20 to optimize OS/2 operations
• Support directly Intel 80387 / Weitek 3167 / Weitek 4167 Floating Point Coprocessors
• Sophisticated DRAM controller:
• Support Fast/Standard page mode DRAM
• Support 4 banks of CPU speed DRAM with memory size up to 64 MB
• Support mixable 256Kx9, 1Mx9, 4Mx9 modules
• Programmable DRAM wait states
• Support 256KB or 384KB (A to F segments of first 1 MB) relocation to the top of DRAM memory
• Support Automatic Memory Size Detection
• 1.0m low-power, high-speed CMOS technology in 160 QFP package

The UM82C482, Integrated System Controller (SC), is part of UMC's high performance 80386/80486 PC/AT chip set. It contains AT bus control logic, data bus conversion logic, CPU reset logic, clock generation for CPU, keyboard and timer, DMA/refresh logic and peripheral interface logic. Incorporated with UM82C481, Integrated Memory Controller IMC), and UM82C206, Integrated Peripheral Controller (IPC), ISC provides system control functions for overall PC/AT computer system.

Features:

• Interface logic for 80386 and 80486 CPUs
• Feedback CPU clock to reduce clock skew and to increase system stability
• Use 1X clock in 80486 mode to ease system design
• Synchronous AT bus clock with programmable CPU clock (divided by 2, 3, 4, 5, 6)
• Programmable CPU clock (divided by 1, 2, 3, 4)
• Programmable keyboard clock (divided by 1.5, 2)
• Separate DMA and refresh request to perform hidden refresh
• DMA interface logic, refresh address counter and control logic
• Fast CPU reset and GATE A20 to optimize OS/2 operations
• Data bus conversion logic between PD and XD buses
• Parity generation and checking logic
• Support 256KB/512KB/1MB EPROMs with single or double EPROM BIOS configuration
• 1.0um low-power, high-speed CMOS technology in 160 QFP package

The 82C206 Integrated Peripheral Controller (IPC) is a single-chip integration of all the main peripheral parts attached to the X bus of PC/AT architecture. The 82C206 replaces the following peripheral logic on motherboards:

• two 8237 DMA controllers
• two 8259A interrupt controllers
• one 8254 timer/counter
• one 146818A-compatible real-time clock
• one 74LS612 memory mapper

Provides:

• Seven DMA channels
• 13 interrupt request channels
• two timer/counter channels

Four DMA transfer modes supported:

• Single
• Block
• Demand
• Cascade

Special Commands provided for ease of programming:

• Clear byte pointer flip-flop
• Set byte pointer flip-flop
• Master clear
• Clear request mask register
• Clear mode register counter

Other features:

• Contains 114 bytes of CMOS RAM
• 8MHz DMA clock with programmable internal divider for 4MHz operation
• 16MB DMA address space
• Programmable wait states for DMA cycles
• Reduced recovery time (120ns) between I/O operations for the 8237, 8259A and 8254
• 84-pin PLCC (plastic leadless chip carrier) or 100-pin QFP (quad flat pack)