OPTi 82C391 (386WB PC/AT)

Description:

Overview

The OPTi-386WB is a highly integrated PC/AT VLSI chipset, for the high end 386-based AT systems. It includes System Controller (SYSC, 82C391), Data Buffer Controller (DBC, 82C392) and Integrated Peripheral Controller (82C206). It is designed for system running from 25 Mhz, 33 Mhz and up to 40 Mhz.

SYSC integrates the write-back cache controller, local DRAM control logic AT bus and CPU interface circuitry. DBC includes the data buffers, AT bus control, decoding logic for keyboard controller, reset and clock generation logic.

A high performance 386-based system can be implemented easily with 386 WB PC/AT chipset.

Features:

  • Two 160-pin CMOS Plastic Flat Package (PFP), and one 84-pin PLCC
  • Copy-Back Direct Mapped Cache with size of 32 KB. 64 KB. 128 KB and 256 KB
  • 16 Bytes Line Size
  • Optional 0/1 Wait State for Cache Write Hit
  • On-chip Comparator for Hit or Miss decision
  • Support 256K/1M/4M DRAM
  • Up to 64 MB Local High Speed Page Mode DRAM memory space
  • Burst Line Fill during Cache Read Miss
  • Two Non-Cacheable Regions Control
  • Option for Cacheable video BIOS
  • Shadow RAM support
  • Hidden Refresh
  • Slow Refresh Support for Laptop Application.
  • 8042 Emulation for Fast CPU Reset and GateA20 generation
  • Turbo/Slow speed Operation
  • AT bus clock . CLK2IN/8 or CLK2IN/6
  • 0 or 1 wait state for 16-bit AT bus cycle
  • CAS# before RAS# refresh to reduce power consumption
Last updated 2019-04-30T00:00:00Z
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