Overview:

The COUGAR II Chip Set provides high integration and a low cost solution for a 25, 33, 50MHz 486/AT based system design. Its flexible architecture allows Burst Mode Direct Mapped Cache Implementation with 64KB/128KB/256KB/512KB cache. The COUGAR II Chip Set combined wilh 82C206 or compatible peripheral controller offer a l00% PC/AT compatible system using less than 20 components plus memory devices. The 82C491 and 82C493 are both available in the 160-pin Plastic Quad Fiat-pad: package. The I.Oμ high speed, low power CMOS Technology allows for substantial chip set stability when running at 33 and 50MHz.

The Chip Set consists of 82C491, and the 82C493. The 82C491 includes 486 CPU control, AT Bus Control, Direct Mapped Cache Control, Page Mode DRAM Control, Synchronous AT Bus Clock Generation, and Clock Switching Logic. The 82C493 contains a data bus conversion logic which performs the conversion necessary between the 8, 16 and 32 bit data paths.

The COUGAR II Chip Set provides very flexible cache based system implementation and a Page Mode DRAM memory to improve performance during read miss cycles. System performance is further enhanced by allowing Refresh and CPU cache hit cycles to occur concurrently without holding the CPU during Refresh cycle.

The COUGAR II is designed to be 100% compatible with the IBM PC/AT. With its optimized Cache and DRAM design, enhanced features like Shadow RAM BIOS and Concurrent Refresh; a high performance/low cost 486/AT can be implemented.

Features:

100% IBM PC/ AT Compatible
Designed to work at 25, 33 and 50MHz on a 486 based system
Flexible architecture to support 64KB, 128KB, 256KB and 512KB Burst Mode Cache Subsystems
Secondary Cache Support Logic on Chip
Up to 64MB DRAM memory support with Page Mode
Unlimited DRAM configurations - Mixing 256K, 1M and 4M devices
Shadow RAM and 256KB Memory Remapping
Software Programmable DRAM Wait States
Single Phase Clock Scheme
Four blocks of non-cacheable memory area
Fast Reset and Gate A20 to optimize OS/2
Support Port 92 Fast Gate A20
Synchronous AT Bus Clock Generation
Weitek 4167 Coprocessor support
Concurrent Refresh and AT Refresh Option
Software Turbo Clock Switching
Less than 20 components plus memory to implement an AT/486 system
1.0 Micron Lmv Power, High Speed CMOS Technology