ET82C491 Cache Controller
The 82C491 contains the Memory Controller, AT Bus Controller, CPU Controller, and clock generation circuitry. The Cache and DRAM Controllers are the main factors affecting the performance/cost ratio of the system. The 80486 has an on-chip 8K cache but a supplemental secondary cache can be easily built by using the 82C49l internal Burst Mode Direct Mapped Controller to reduce read cycle access time if the requested data is not currently stored in the on-chip cache. A Page Mode DRAM Controller further increases the performance by compensating for the time spent during the read miss cycle.
The 82C491 interfaces directly with the 80486 and implements the state machines required for controlling all bus accesses. The AT Bus Clock is synchronous with the processor clock and generated through a clock divider to insure that the system is 100% IBM compatible.
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