Description:

VL82C325 386sx System Cache Controller

The VL82C325 Memory Cache Controller is a high performance; highly integrated cache controller for systems based on the VLSI Technology, Inc.'s TOPCAT 386SX or SCAMP-LT chip sets. To implement a 32KB two-way set associative cache subsystem, all that is required is the VL82C325 and two 8K x 16 cache data RAMs. The VL82C325 has been designed to be an integral part of the TOPCAT386SX chip set. this feature improves the overall system performance by reducing the number of wait states during non-cache cycles when compared to cache controllers which must pipeline all cycles which can not be serviced by reading from the cache data RAM. The VL82C320A TOPCAT System Controller or the VL82C310 SCAMP Controller, and the VL82C325 operate in parallel to decode 386SX requests. The controller starts decoding the 386SX cycle simultaneously with the VL82C325 and is therefore able to actually start a memory cycle before a miss indication is generated by the VL82C325.

Features:

• Optimized for TOPCAT 386SX and SCAMP-LT chip sets
• Improved i386SX and AMD386SX system performance:
  • Fast look-aside architecture
  • Zero wait state read-hit access
  • Reduces average processor wait states to near zero
• Multiple cache organizations
  • Two-way set associative: 16KB
  • Two-way set associative: 32KB
• Memory update strategy
  • Write-thru
• Least recently used (LRU) replacement algorithm
• Integrates complete cache directory on-chip
• Supports memory configurations to 16 MB
• Programmable cache architecture
  • Block size: 8 or 16 bytes
  • Line size: 2 bytes
  • Update strategies: single cycle (one line)
• Write-protect region support
  • Write-protect regions (#): 256
  • Write-protect region size: 2KB between 512K and 1M
• Non-cacheable region support
  • Non-cache regions (#): 504
  • Non-cacheable region size: 64KB below 512K 2KB between 512K and 1M 64KB above 1M
• 25 MHz operation
• Optimized for one or two dual 4K x8 cache data RAMs
• Operates both in pipelined and in non-pipelined modes
• Built-in self-test and cache data RAM testability features
• Auto-flush on EMS-update events
• 100-lead MQFP