Description:

The Pixel Data Manager (PDM) of the WD9500 chip set contains:

Data Processor (DP), which is responsible for updating VRAM in support of drawing and data transfer operations and altering pixel data (color values) according to masks and parameters, including "mix" specifications supplied in shared internal registers by the DP and GP. The DP receives pixel data on a bidirectional bus from the VRAM, modifies it, and then writes it back to the VRAM on the same bus.

Display Processor (DSP), which manages the DAC and monitor, coordinating its role in the screen refresh process with the MIC. With an integrated back-end VRAM design, the DSP serializes and multiplexes pixel data ("pumped" out of VRAM by the MIC) to the DAC in synchronization with the timing of the monitor's sweep across the display screen. (With external back-end support, this DSP function is assumed by external logic within the VRAM block and the DAC).