Also known as:

• Silicon Image SiI0646

Description:

Overview

CMD Technology introduces the PCI0646, the world's first PCI to IDE controller chip supporting high-speed PIO and bus master data transfers. This chip is designed to offer a simple, cohesive upgrade path from the highly successful PCI0640B PIO-only chip to the new PCI0646 PIO/DMA chip, ensuring optimal performance and compatibility with the latest operating systems and disk drives.

Key Features:

• High-speed PIO and bus master data transfers
• Up to 20 MB/Sec transfer rates in DMA mode, up to 16.8 MB/Sec in PIO mode
• Supports bus master DMA at 133 MB/Sec PCI burst rate
• 100-pin PQFP
• Fully supports ATAPI DMA/PIO transfers
• Compatible with CMD's IDE Tape Commander
• One circuit board schematic for PCI0640B, PCI0643, and PCI0646
• 2 channels, supporting up to 4 IDE drives
• Surpasses and supports Enhanced IDE and Fast PIO timing modes 3, 4, and beyond
• Supports multi-word and single-word DMA timing modes 0, 1, 2, and beyond
• Supports DMA and PIO RAID transfers, compatible with CMD's WinRAID and Advanced WinRAID software products
• Fully supports the latest PCI-IDE specification and all Plug-and-Play (PnP) specifications

The PCI0646 chip is designed to be fully compatible with all existing IDE drives and software drivers. CMD's intelligent, high-speed drivers identify all connected IDE devices and optimize the data transfer parameters for maximum performance. The chip supports up to four IDE drives through its two-channel architecture and meets or exceeds the specifications of the ATA-2 standard.

Hardware Bugs

The CMD 646 chip, along with the original CMD 640, is known to have data corruption bugs. These bugs are similar to those found in the PC Tech RZ1000 chipset, which was used in a number of motherboards, including those from Intel. Both CMD 640 and CMD 646 chips were affected by these issues, resulting in data corruption on some systems.

To address the data corruption issues, modern operating systems implement a workaround by disabling aggressive acceleration mode. This solution, however, results in a performance loss of about 10%. Although the workaround helps to prevent data corruption, it comes at the cost of reduced performance for systems using the CMD 646 chip.

By looking at the Linux driver code for the CMD64x series chips we can determine that the CMD640 PCI PATA controller includes a few workarounds to address known data corruption issues in the CMD64x chips:

• Disabling aggressive acceleration mode: The driver configures the controller to use a slower and more conservative mode by modifying the control register settings in the cmd640_hardware_init function. This helps to prevent data corruption at the cost of losing about 10% of performance.

• Timing adjustments: In the cmd640_set_piomode function, the driver carefully calculates and adjusts the timings for setup, active, and recovery periods based on the specific ATA device and its mode. These adjustments help to ensure that data transfers are reliable and stable, minimizing the risk of data corruption.

• Handling shared timings on the second channel: In the cmd640_qc_issue function, the driver dynamically updates the active and recovery timings for devices on the second channel when switching between them. This is done to account for the shared timing settings on this channel, which helps to maintain stable data transfers and reduce the risk of data corruption.

These workarounds aim to minimize the impact of known data corruption issues in the CMD64x chips while still maintaining acceptable performance levels.

Source: https://github.com/torvalds/linux/blob/master/drivers/ata/pata_cmd640.c