Description:

82352DT EISA Bus Buffer (EBB):

The 82352DT design allows it to replace the multiple address and data latch-buffer/driver ICs used in EISA applications. The EBB provides three modes of operation: a 32-bit mode without parity to replace the EISA data swap buffers, a 32-bit mode with parity to replace the EISA DRAM data parity buffers, and an EISA address mode to replace the host to EISA/ISA address buffers. Mode 2 on the EBB is reserved. The same chip is strapped in three different ways to obtain the three configurations.

Features:

• Designed Specifically for EISA Bus Requirements
• Provides Three Modes of Operation
  • Data Latch and Swap Functions Allow Swapping and Assembly of Data between the Host and EISA/ISA Buses on a Byte by Byte Basis (Mode 0)
  • Provides a Buffered Path with Parity Generation/Check between the Host Data Bus and DRAM (Mode 1)
  • Address Latch Functions Provide Latching between the Host andEISA/ISA Buses (LA and SA Addresses) (Mode 3)
• 120-Pin Quad Flat Pack (QFP)
• Similar in Function to Discrete Implementation Using 74F543s/544, 74180s, and 74ALS245s
• Replaces 19 Discrete Components
  • Three 82352DTs are Used Per 82350 EISA System
• The 82352DT Interfaces Easily to the System
  • Buffer Control for the 32-Bit Mode W/O Parity and the EISA Address Mode is Provided by the 82358 (EISA Bus Controller)
• The 82352 and 82352DT are Socket Compatible
• The 82352DT is Designed to Meet All of the 82352 Specifications