Description:

82EC392 Data Buffer Controller (DBC)

The 82EC392 performs all of the data buffering functions. Under the control of the processor, the 82EC392 routes data to and form the local CPU Bus.

The DBC performs Data Bus Conversion when CPU accesses to 16 or 8 bit device through 32/16 bit instruction. The bus conversion is also supported for DMA/Master cycle for the transfer between local DRAM or cache memory and devices which resides on AT bus.

Parity Generation/Detection Logic will compare the parity bit and the parity generated from the data byte. If a mismatch happens, the parity error will be generated.

In order to reduce the components count, DBC provides the clock sources for the timer of 8OC206 and 8042 Keyboard Controller.

The DBC also monitors both the PWGDS# (Powergood) signal from power supply and reset signal from the reset switch. The DBC provides the Numeric Coprocessor support for 387 and 3167 without external logic components.

In addition, the DBC provides Chip Select for Keyboard Controller and RTC, Keyboard Reset and Gate A20Emulation Logic, Speaker Control, and NMI Logic.