Description:

VL82C320A System Controller

The VL82C320/VL82C320A contains the System Control and the Data Buffering functions in a 160-lead quad flatpack. The System Controller is designed to perform in 80286- and 80386SX-based systems with clock speeds of 25 MHZ and below, and peripheral bus speeds up to 12MHz. The System Controller functions are highly programmable via a set of internal configuration registers. Defaults on reset for the configuration registers mimic the compatibility requirements of the original IBM PC/AT as closely as possible. The power-up defaults allow any possible configuration of the system to boot at the CPU's rated speed.

The System Controller handles system board refresh directly and controls the timing of slot bus refresh that is actually performed by the VL82C331 ISA Bus Controller. Refresh may be performed in coupled or decoupled mode. The former method is the standard PS/AT- compatible mode where on- and off-board refreshes are independent. Both may be programmed for independent, slower than normal rates. This allows the use of low-power, slow refresh DRAMs. The VL82C320/VL82C320A controls all timing in both modes. In all cases, refreshes are staggered to minimize power supply loading and attendant noise on the VDD and ground pins. In sleep mode, refresh switches to CAS before RAS refresh for maximum power savings. the physical banks of DRAM can be logically reordered through one of the indexed configuration registers. this DRAM remap option is useful n order to map out bad DRAM banks allowing continued use of a system until repairs are convenient. It also allows DRAM bank combinations not in the supported memory maps to be logically moved into a supported configuration with-out physically moving memory components.