Also known as:

• Micron MI9382

Description:

82C382 Cache Controller

The 82C382D performs the Memory Management functions for the HiD/AT chipset. It is designed to optimize cost of high performance 386/AT systems with 64KB, l28KB or larger Direct Mapped Cache Memory. It also implements logic to maintain compatibility in the AT environment . It provides a Page Interleave backend for main DRAM memory, in order to improve performance during miss cycles. It also has features for reducing system cost.

It minimizes Cache Memory cost by allowing the use of slow SRAM; by supporting single EPROM BIOS configurations; putting DRAM on the local bus and consequently reducing DRAM speeds by 15ns typically; and by remapping 256K of DRAM between 640K and 1024K to top of main memory.

It provides a very flexible implementation of paging for the main DRAM memory. For even bank configurations, it provides 2-way or 4-way interleaving; for odd banks it provides paging. This provides a flexible approach to increasing the size of the local memory as software demands increase, without imposing a penalty on performance.

Finally, memory performance is optimized by shadow RAM techniques for BIOS ROMs; concatenated pages for multiple hank configurations; paging for odd banks; and variable page size for larger DRAMs.

Versions:

• 82C382D-25 (25Mhz)
• 82C382D-33 (33Mhz)
• 82C382-B (20, 25, 33Mhz)