Description:

82C295 SLCWB

The OPTi SLCWB Chipset provides a highly integrated solution for fully compatible, high-performance PC/AT platforms. Since the chipset is so critical to the performance and cost structure of a PC, this highly integrated approach provides the foundation for a very cost effective platform without compromising performance. Together with OPTi's 82C206 Integrated Peripherals Controller (IPC), this silicon will support the IBM 486SLC2, Intel/AMD 386SX and Cyrix CX486SLC microprocessors in the most cost effective and power efficient designs available today. This chipset offers optimum next generation performance for systems running up to 40MHz. The OPTi SLCWB solution provides the performance benefits of a 32-bit programming architecture with the cost savings associated with 16-bit hardware systems. The OPTi SLCWB Chipset provides a solution positioned to deliver value, without neglecting quality, compatibility, or reliability.

The 82C295 integrates a write-back cache controller, a local DRAM controller, the CPU state machine, the AT bus state machine, and data buffers all in a single 160-pin Plastic Quad Flat Pack (PQFP). On-chip hardware provides the hooks for local bus device support.

Features:

• 100% IBM PC/AT compatible SX chipset
• Supports IBM 486SLC2 microprocessor
• Two chip PC/AT solution:
  • 82C295 System Controller, 160-pin PQFP (Plastic Quad Flat Package)
  • 82C206 Integrated Peripherals Controller, 84-pin PLCC (Plastic Leaded Chip Carrier)
• Supports systems running from 16 to 40MHz
• Write-back direct-mapped cache with programmable size selections: 16KB, 32KB, 64KB, 128KB
• Supports four banks of 256KB, 1MB, and 4MB page mode local DRAMs for configurations up to 16MB
• Two programmable non-cacheable regions
• Programmable cache and DRAM read/write cycles
• Cache coherency (for IBM SLC2) is achieved through discrete cycle/line invalidate bus snooping
• Hidden refresh, slow refresh, and CAS-before-RAS refresh supported
• Shadow RAM option for system and channel ROM BIOS
• High performance local bus support includes DMA/ISA master to local bus support
• Turbo/slow speed selection
• Synchronous AT bus clock with programmable clock division options: CLK2/4, /6, /8, or /10
• Zero or one wait state options for 16-bit AT bus cycles
• Transparent 8042 emulation for fast CPU reset and GATEA20 generation
• Supports the 80387SX numerics coprocessor
• Option for write protected, cacheable video BIOS
• Flash ROM support
• Combined system/video ROM support
• Low power, high speed 1.0-micron CMOS technology