Description:

82C282 Cache Sx/AT (Write Through Cache)

The 82C282 is a highly integrated AT system logic VLSI for high end 386 Sx AT systems. It integrates the logic for local DRAM control, AT bus control, cache memory control, and data bus control and is designed for systems running at 16MHz, 20MHz, and 25MHz.

A high performance, compact 386 Sx/AT system can be implemented easily with 82C282 and standard peripheral controllers like the 82C206 or the VLSI 82C100 plus Dallas Semiconductor DS1287.

Features:

• Flexible DRAM Banks Configuration
  • The 82C282 supports 256K, 1M, and 4M memory devices, total main memory size can be up to 16MB. A total of 12 different memory configurations are supported.
• Page Mode Operation
  • Based on the memory configuration shown above [see datasheet], the memory control unit inside the 820282 performs page mode of operation with a varying block size of 1k, 2k, or 4k bytes for 256k, 1M, or 4M DRAMs respectively.
• System BIOS Shadow RAM
  • The 820282 memory control unit provides shadow RAM feature for several areas of memory system BIOS, video BIOS, and adapter BIOS.
• Memory Remapping
  • If shadow RAM feature is not utilized for the memory area between 0D0000H - 0EFFFFH, then memory remapping is possible. The local DRAM areas, 0A0000H - 0BFFFFH and 0D0000H - 0EFFFFH, a total of 256 KByte, are remapped to the top of total system memory. The areas for 0F0000H-0FFFFFH (system BIOS) and 0C000H-0CFFFFH (Video BIOS) are reserved for shadow RAM purpose.
• Flexible Multiplexed DRAM Address
• Cache Control Subsystem
  • Direct-mapped posted write cache control function provides a low cost alternative to enhance the system performance by up to 50%. In order to simplify the design without increasing the system cost or decreasing performance, the 82C281/2 has been designed to support only non-pipeline mode for systems with cache memory.The 82C282 offers the following cache control features:
    • Flexible Cache Memory Size
      • 4MB Cacheabie main memory by using 16KB low cost SRAM.
      • 8MB Cacheable main memory by using 32KB low cost SRAM.
      • Cache 16MB main memory by using 64KB low cost SRAM.
      • Increase the cache size beyond 64KB up to 512KB
    • Cache Line Size 4 Byte
      • Burst mode memory prefetch is supported by the 82C282. During cache read miss cycles, the memory control subsystem will perform two consecutive read cycles to fetch 4 bytes from main memory before terminating the cycle by sending RDYO# signal to 3868X.
    • Non-Cacheable Area. The non-cacheable areas are predefined as indicated below:
      • I/O address space
      • memory address between 0A0000H and 0FFFFFH.
      • any memory address beyond the current configured memory size.
      • programmable non-cacheable memory area as defined by 82C281/2 internal registers.
    • 820282 Write Through Cache
      • The 820282 supports a write-through cache system which allows the designer to reduce system cost by eliminating two F244's and two F373's with only a slight reduction in system performance (5-10%).
    • AT Bus Control
      • The 820282 AT bus control unit handles all of the AT bus operations and the DMA/Refresh arbitration. The AT bus control unit supports the following features:
        • Programmable AT Bus Clock. The AT bus clock, ATCLK. can be programmed as CLK2/6, which is default, or CLK2/4.
        • Turbo Switch. The 820282 provides a turbo switch feature that allows users to change the system clock speed. A programmable bit will enable or disable this turbo function. When the turbo function is enabled by setting reg[14H], bit[1] to 1, the 82C282 turbo pin then determines the system clock speed. A low on the turbo pin forces the CPU to run at the current AT bus speed which IS CLK2/6 or CLK2/4.