Overview

The 82430NX PCIsets provide the Host/PCI bridge, cache/main memory controller, and an I/O subsystem core (either PCI/EISA or PCI/ISA bridge) for the next generation of high-performance personal computers based on the Pentium processor. System designers can take advantage of the power of the PCI Local bus for the local I/O while maintaining access to the large base of EISA and ISA expansion cards, and corresponding software applications. Extensive buffering and buffer management within the bridges ensures maximum efficiency in all three bus environments (Host CPU, PCI, and EISA/ISA Buses).

The 82430NX PCIset consists of the 82434NX PCI/Cache Memory Controller (PCMC) and the 82433NX Local Bus Accelerator (LBX) components, plus, either a PCI/ISA bridge or a PCI/EISA bridge. For an ISA-based system, the 82430NX PCIset includes the 82378ZB System I/O (SIO) component as the PCI/ISA bridge. For the DP ISA based system, the 82430NX PCIset includes the 82379AB. For UP or DP EISA-based systems, the 82430NX PCIset includes the 82375EB/SB PCI/EISABridge (PCEB) and the 82374EB/SB EISA System Component (ESC).

Features:

Supports the Pentium Processor at iCOMP Index 735\90 MHz, Pentium Processor iCOMP Index 815\100 MHz, and Pentium Processor iCOMP Index 610\75 MHz
Supports Uni-Processor (UP) or Duel-Processor (DP) Configurations
Interfaces the Host and Standard Buses to the PCI Local Bus
- Up to 132 MBytes/Sec Transfer Rate
- Full Concurrency Between CPU Host Bus and PCI Bus Transactions
Integrated Cache Controller Provided for Optional Second Level Cache
- 256 KByte or 512 KByte Cache
- Write-Back Policy (82430NX)
- Standard or Burst SRAM
Integrated Tag RAM for Cost Savings on Second Level Cache
Supports the Pipelined Address Mode of the Pentium Processor for Higher Performance
Provides a 64-Bit Interface to DRAM Memory
- From 2 MBytes to 512 MBytes of Main Memory
- 70 ns and 60 ns DRAMs Supported
Optional ISA or EISA Standard Bus Interface
- Single Component ISA Controller
- Two Component EISA Bus Interface
- Minimal External Logic Required
Supports Burst Read and Writes of Memory from the CPU and PCI Buses
Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
Host CPU Writes to PCI Converted to Zero Walt-State PCI Bursts with Optional TROY # Connection
Integrated Low Skew Host Bus Clock Driver for Cost and Board Space Savings
PCIset Operates Synchronous to the CPU and PCI Clocks
Byte Parity Support for the Host and Main Memory Buses
- Optional Parity on the Second Level Cache