IBM AT chipset
Chipset parts: Texas Instruments SN74LS612N (Memory Mapper) Intel 82284 (Clock Generator and Ready Interface) Intel 82288 (Bus Controller) Intel 8254-2 (Programmable Interval Timer) Intel 8237A-5 (DMA Controller) Intel 8042 (Keyboard Controller) Intel 8259A-2 (Programmable Interrupt Controller) Motorola MC146818P (Real-Time Clock + RAM) (any brand) Discrete Logic


The original chipsets used by IBM for the AT are based on the Intel iAPX 286 system. Some additional components are taken from the MCS-80/85 system. The iAPX 286 system consists of the 80286 CPU and support chips.

The chips used in the AT were introduced by Intel at various different times over approximately a decade between 1975 and 1984. In addition there are various different revisions of a particular chip. Due to these differences, relying on a datasheet from a particular year alone, may be insufficient. One thing that should be noted is the the A on the end of a part number is significant. If you click the encyclopedia link you can find a very detailed summary of the differences between the datasheets up to 1989. Using very early versions of chips manufactured before the introduction of the AT may cause unpredictable results.

Documented parts

TI SN74LS612N Memory Mapper

Each 'LS612 memory mapper integrated circuit contains a 4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of 2-line to 1-line multiplexers, and other miscellaneous circuitry on a monolithic chip.

The memory mappers are designed to expand a microprocessor's memory addressing capability by eight bits. Four bits of the memory address bus can be used to select one of 16 map registers that contain 12 bits each. these 12 bits are presented to the system memory address bus through the map output buffers along with the unused memory address bits from the CPU. However, addressable memory space without reloading the map registers is the same as would be available with the memory mapper left out. The addressable memory space is increased only by periodically reloading the map registers from the data bus. This configuration lends itself to memory utilization of 16 pages of 2^(n-4) registers each without reloading (n - number of address bits available from CPU).

  • Expands 4 Address Lies to 12 Address Lines
  • Designed for Paged Memory Mapping
  • Output Latches Provided on 'LS610
  • 3-State Map Outputs
  • Compatible with TMS9900 and Other Microprocessors

Intel 82284 Clock Generator and Ready Interface

The 82284 is a clock generator/driver which provides clock signals for iAPX 286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with hysteresis.

  • Generates System Clock for iAPX 286 Processors
  • Uses Crystal or TTL Signal for Frequency Source
  • Provides Local READY and Multibus READY Synchronization
  • 18-pin Package
  • Single +5V, Power Supply
  • Generates System Reset Output from Schmitt Trigger Input
  • Available in EXPRESS
    • Standard Temperature Range
    • Extended Temperature Range

Intel 82288 Bus Controller


  • 82288 8MHz c:83
  • 82288-6 6MHz c:84
  • 82288-8 8MHz c:89
  • 82288-10 10MHz c:89
  • 82288-12 12.5MHz c:89

The Intel 82288 Bus Controller is a 20-pin HMOS component for use in iAPX 286 microsystems. The bus controller provides command and control outputs with flexible timing options. Separate command outputs are used for memory and I/O devices. The data bus is controlled with separate data enable and direction control signals.

Two modes of operation are possible via a strapping option: Multibus compatible bus cycles, and high speed bus cycles.

  • Provides Commands and Control for Local and System Bus
  • Offers Wide Flexibility In System Configurations
  • Flexible Command Timing
  • Optional Multibus Compatible Timing
  • Control Drivers with 16 ma Iol and 3-State Command Drivers with 32 ma Iol
  • Single + 5V Supply
  • Available in 20 Pin Cerdip Package

Intel 8254-2 Programmable Interval Timer


  • 8254 8MHz c:81
  • 8254-2 10MHz c:81
  • 8254-5 5MHz c:86

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.

The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

  • Compatible with all Intel and most other microprocessors
  • Handles Inputs from DC to 10 MHz
    • 5 MHz 8254-5
    • 8 MHz 8254
    • 10 MHz 8254-2
  • Six Programmable Counter Modes
  • Status Read-Back Command
  • Three Independent 16-bit Counters
  • Binary or BCD Counting
  • Single +5V Supply
  • Uses HMOS Technology
  • Available in EXPRESS Standard Temperature Range

Intel 8237A-5 DMA Controller


  • 8237A - 3MHz
  • 8237A-4 - 4MHz
  • 8237A-5 - 5MHz (compatible with PC/XT/AT)

Note, the 8237A family is not the same as the 8237 family, which is older.

The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. Memory-to-memory transfer capability Is also provided. The 8237A offers a wide variety of programmable control features to enhance data throughput and system optimization and to allow dynamic reconfiguration under program control.

The 8237A Is designed to be used in conjunction with an external 8-bit address register such as the 8282. It contains four independent channels and may be expanded to any number of channels by cascading additional controller chips.

The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be individually programmed to Autoinitialize to its original condition following an End of Process (EOP).

Each channel has a full 64K address and word count capability.

The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected versions of the standard 3 MHz 8237A respectively.

  • Enable/Disable Control of Individual DMA Requests
  • Four Independent DMA Channels
  • Independent Autoinitialization of all Channels
  • Memory-to-Memory Transfers
  • Memory Block Initialization
  • Address Increment or Decrement
  • High Performance: Transfers up to 1.6M Bytes/Second with 5 MHz 8237A-2
  • Directly Expandable to any Number of Channels
  • End of Process Input for Terminating Transfers
  • Software DMA Requests
  • Independent Polarity Control for DREQ and DACK Signals

Intel 8042 Keyboard Controller:

mR_Slug notes:

This is the Intel UPI-42 (Universal Peripheral Interface 8042) programed as a keyboard controller and additional functions. It was released around '82. The 8042 is a ROM mask (programmed at the factory). It is pin compatible with the 8042AH and EPROM based 8742AH.

An 8042 will NOT function as a keyboard controller UNLESS it is programed to do so. Programs can differ between 8042's. In this application, for FULL OPERATION in a motherboard the program MUST be correct. Typically, swapping an 8042 from a PC to another, will often provide a functional keyboard, the additional functions may not work. It may be labeled as 'Keyboard BIOS'. Using an 8042 programmed for some other (non-PC) application will NOT work.

Intel 8042 Universal Peripheral Interface:

The Intel UPI-42 is a general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control.

They are essentially "slave" microcontrollers, or microcontrollers with a slave interface included on the chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family, as well as other 8-, 16-bit systems.

To allow full user flexibility, the program memory is available in ROM, One-Time Programmable EPROM (OTP) and UV-erasable EPROM. All UPI-42 devices are fully pin compatible for easy transition from prototype to production level designs, These are the memory configurations available.

  • UPI-42: 12 MHz
  • Pin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products
  • 8-Bit CPU plus ROM/EPROM, RAM, I/O, Timer/Counter and Clock in a Single Package
  • 2048 x 8 ROM/EPROM, 256 x 8 RAM on UPI-42, 8-Bit Timer/Counter, 18 Programmable I/O Pins
  • One 8-Bit Status and Two Data Registers for Asynchronous Siave-to-Master Interface
  • DMA, Interrupt, or Polled Operation Supported
  • Fully Compatible with all Intel and Most Other Microprocessor Families
  • Interchangeable ROM and EPROM Versions
  • Expandable I/O
  • Sync Mode Available
  • Over 90 Instructions: 70% Single Byte
  • Available in EXPRESS
    • Standard Temperature Range
  • Intelligent Programming Algorithm
    • Fast EPROM Programming
  • Available in 40-Lead CERDIP, 40-Lead Plastic and 44-Lead Plastic Leaded Chip Carrier Packages

Intel 8259A-2 Programmable Interrupt Controller

mR_Slug notes:

Briefly the differences between the variants:

  • 8259A Data Valid From RD/INTA: Max 200ns c:79
  • 8259A-2 Data Valid From RD/INTA: Max 120ns c:81 compatible with PC/XT/AT
  • 8259A-8 Data Valid From RD/INTA: Max 300ns c:79

It's quickest to replace like with like. Note the non-A version has many more differences to the A versions. For a summary of differences see the following link, or consult the datasheets.

mR_Slug Intel Chip Specifications 1975 - 1989

Intel 8259A Programmable Interrupt Controller

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single +5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

  • 8086, 8088 Compatible
  • MCS-80, MCS-85 Compatible
  • Eight-Level Priority Controller
  • Expandable to 64 Levels
  • Programmable Interrupt Modes
  • Individual Request Mask Capability
  • Single + 5V Supply (No Clocks)
  • 28-Pin Dual-In-Line Package
  • Available in EXPRESS
    • Standard Temperature Range
    • Extended Temperature Range

Motorola MC146818P Real-Time Clock + RAM:


  • MC146818P - plastic DIP
  • MC146818C - plastic DIP extended temp range.


  • MC146818A? - QFP (Datasheet states it is available, no p/n)
  • MC146818AC - plastic DIP extended temp range.
  • MC146818AL - ceramic DIP
  • MC146818AP - plastic DIP
  • MC146818AS - CERDIP
  • MC146818AF - SOP
  • MC146818AFN - PLCC

The A variant is newer. It has two additional pins, 1 and 16 that are NC on the non-A. Pin 1 is MOTEL, Tying it high or low determines if the chip uses Motorola or competitor e.g. Intel timing. Pin 16 is Standby. This was previously handled by the chip enable pin in the non-A. Details can be found on page 11 of both datasheets.

Functionally, in the PC architecture they are all the same, just different packages and temp ratings.

The MC146818 Real-Time Clock plus RAM is a peripheral device which includes the unique MOTEL concept for use with various microprocessors, microcomputers, and larger computers. This part combines three unique features: a complete time-of-day clock with alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static RAM. The MC146818 uses high-speed CMOS technology to interface with 1MHz processor busses, while consuming very little power.

The Real-Time Clock plus RAM has two distinct uses. First, it is designed as a battery powered CMOS part (in an otherwise NMOS/TTL system) including all the common battery backed-up functions such as RAM, time, and calendar. Secondly, the MC146818 may be used with a CMOS microprocessor to relieve the software of the timekeeping workload and to extend the available RAM of an MPU such as the MC146805E2


  • Low-Power, High-Speed, High-Density CMOS
  • Internal Time Base and Oscillator
  • Counts Seconds, Minutes, and Hours of the Day
  • Counts Days of the Week, Date, Month, and Year
  • 3 V to 6 V Operation
  • Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
  • Time Base Oscillator for Parallel Resonant Crystals
  • 40 to 200 uW Typical Operating Power at Low Frequency Time Base
  • 4.0 to 20 mW Typical Operating Power at High Frequency Time Base
  • Binary or BCD Representation of Time, Calendar, and Alarm
  • 12- or 24-Hour Clock with AM and PM in 12-Hour Mode
  • Daylight Savings Time Option
  • Automatic End of Month Recognition
  • Automatic Leap Year Compensation
  • Microprocessor Bus Compatible
  • MOTEL Circuit for Bus Univerality
  • Multiplexed Bus for Pin Efficiency
  • Interfaced with Software as 64 RAM Locations
  • 14 Bytes of Clock and Control Registers
  • 50 Bytes of General Purpose RAM
  • Status Bit Indicates Data Integrity
  • Bus Compatible Interrupt Signals (IRQ)
  • Three Interrupts are Separately Software Maskable and Testable
    • Time-of-Day Alarm, Once-per-Second to Once-per-Day
    • Periodic Rates from 30.5 us to 500 ms
    • End-of-Clock Update Cycle
  • Programmable Square-Wave Output Signal
  • Clock Output May Be Used as Microprocessor Clock Input
    • At Time Base Frequency /1 or /4
  • 24-Pin Dual-In-Line Package

Various Brands of Discrete Logic

A significant portion of this chipset is implemented in discrete logic. This typically refers to 7400 TTL DIP packages, but on more modern boards this may be surface-mount and/or include other family's. In this context it could include PALs, GALs, Gate Arrays and other chips that have either not been identified, or are not major chips.


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