Overview

It's implemented with the 82C283 and a standard peripheral controller like OPTi/C&T 82C206 or the VLSI 82C100.

Documented parts

• 82C283
• 82C206

82C283 386SX System Controller

The 82C283 is a highly integrated, AT system logic VLSI chip for high-end 386SX/AT systems. It integrates a local memory controller (local memory is on-board memory), AT bus controller, and data bus controller into one chip. It is designed for systems running at 16MHz, 20MHz, 25MHz, and 33MHz*. A high performance, compact 386SX/AT system is readily implemented with the 82C283 and a standard peripheral controller like OPTi's 82C206 or the 82C100 (with Dallas Semi-conductor (DS1287).

*Rev B Only

Versions:

• 82C283A 16-25MHz
• 82C283B 16-33MHz

Features:

• Flexible DRAM banks configuration
  • Supports 256K, 1M and 4M DRAM modules (16MB total)
• Block interleave mode operations
  • Block interleaving at a block size of 512 bytes
• BIOS shadow RAM
  • Shadow RAM for system, video and adapter BIOS
• Memory remapping
• Flexible multiplexed DRAM address
• Programmable AT bus clock
• Turbo switch
• 160-pin PQFP (Plastic Quad Flat Pack)

The 82C206 Integrated Peripheral Controller (IPC) is a single-chip integration of all the main peripheral parts attached to the X bus of PC/AT architecture. The 82C206 replaces the following peripheral logic on motherboards:

• two 8237 DMA controllers
• two 8259A interrupt controllers
• one 8254 timer/counter
• one 146818A-compatible real-time clock
• one 74LS612 memory mapper

Provides:

• Seven DMA channels
• 13 interrupt request channels
• two timer/counter channels

Four DMA transfer modes supported:

• Single
• Block
• Demand
• Cascade

Special Commands provided for ease of programming:

• Clear byte pointer flip-flop
• Set byte pointer flip-flop
• Master clear
• Clear request mask register
• Clear mode register counter

Other features:

• Contains 114 bytes of CMOS RAM
• 8MHz DMA clock with programmable internal divider for 4MHz operation
• 16MB DMA address space
• Programmable wait states for DMA cycles
• Reduced recovery time (120ns) between I/O operations for the 8237, 8259A and 8254
• 84-pin PLCC (plastic leadless chip carrier) or 100-pin QFP (quad flat pack)