Intel 450KX (PCIset KX Orion WS/Mars)

Description:

The Intel 450KX PCIset provides a high-performance system solution for PentiumĀ® Pro processor-based PCI systems by combining high integration, high performance technology with a scalable architecture that is capable of high throughput for up to two Pentium Pro processors. Scalability provides a wide range of system solutions from cost-effective uniprocessor systems to high-end multiprocessor systems without sacrificing performance. For systems requiring extensive I/O (e.g., file servers), a second PB can be easily added providing two high-performance PCI bus structures. The flexibility of the memory controller permits easy expansion from a simple non-interleaved organization to a 2-way or 4-way interleaved organization to increase performance. Extended error checking and logging, ECC, and the ability to build in redundancy (e.g., multiple processors and dual PCI bridges) provides a comprehensive solution for systems requiring high reliability.

The Intel 450KX desktop PCIset consists of the following parts:

  • 82454KX PCI Bridge (PB)
  • Memory Controller (MC)
    • 82453KX DRAM Controller (DC)
    • 82452KX Data Path (DP)
    • (4x) 82451KX Memory Interface Components (MIC)

The system configuration using the Intel 450KX PCIset supports one PB, one MC and up to two Pentium Pro processors. An ISA subsystem is also located below the PB. For Pentium Pro processor bus error detection, the 450KX generates and checks parity over the address and request/response signal lines. This feature can be enabled/disabled during system configuration.

The combined MC (DC, DP, and four MICs) act as one physical load on the Pentium Pro processor bus. The DC provides control for the DRAM memory subsystem, the DP provides the data path, and the four MICs are used to interface the MC data path with the DRAM memory subsystem. The memory configuration can be either 2-way inter1eaved or non-inter1eaved. Both single-sided and double-sided SIMMs are supported. DRAM technologies up to 64 Mb at speeds of 50ns, 60ns, and 70ns can be used. Asymmetric DRAM is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 columns address lines). The maximum memory size is 1 GB for the 2-way inter1eaved configuration and 512 Mbytes for the non-inter1eaved configuration using 16 Mbit technology. In addition to these memory configurations, the MC provides data integrity features including ECC in the memory array. These features, as well as a set of error reporting mechanisms, can be selected via configuration of the MC. Each inter1eave provides a 64-bit data path to main memory (72-bits including ECC).

The MC is PC compatible. All ISA and EISA regions are decoded and shadowed based on programmable configurations. Regions above 1 Mbyte with size 1 Mbyte or larger that are not mapped to memory may be reclaimed by setting the appropriate configuration in the MC. Three programmable memory gaps can be created and are called the Low Memory Gap Region, the Memory Gap Region and the High Memory Gap Region.

Last updated 2024-03-14T21:51:00Z
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