The Intel 430TX PCIset (430TX) consists of the 82439TX System Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4).
The 430TX supports both mobile and desktop architectures. The 430TX forms a Host-to-PCI bridge and provides the second level cache control and a full function 64-bit data path to main memory.
The MTXC integrates the cache and main memory DRAM control functions and provides bus control to transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a writeback cache policy for cache sizes of 256 Kbytes and 512 Kbytes.
The cache memory can be implemented with pipelined burst SRAMs or standard SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. For the MTXC DRAM controller, six rows are supported for up to 256 Mbytes of main memory.
The MTXC is highly integrated by including the Data Path into the same BGA chip. Using the snoop ahead feature, the MTXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the MTXC integrates posted write and read prefetch buffers. The 430TX integrates many Power Management features that enable the system to save power when the system resources become idle.
PCI 2.1 Compliant
Supports the Universal Serial Bus (USB 1.1)
Integrated Data Path (Host Bus <=> DRAM <=> PCI) on die
Integrated DRAM Controller
- 4 Mbytes to 256 MBytes main memory
- 64-Mbit DRAM/SDRAM Technology Support
- FPM (Fast Page Mode), EDO and
- SDRAM DRAM Support
- 6 RAS Lines Available
- Integrated Programmable drive Strength for DRAM Interface
- CAS-Before-RAS Refresh, Extended Refresh and Self Refresh for EDO
- CAS-Before-RAS and Self Refresh for SDRAM
Integrated L2 Cache Controller
- 64-MB DRAM Cacheability
- Direct Mapped Organization (Write Back Only)
- Supports 256K and 512K Pipelined Burst SRAM and standard SRAM
- Cache Hit Read/Write Cycle Timings at 3-1-1-1
- Back-to-Back Read/Write Cycles at 3-1-1-1-1-1-1-1
- 64K x 32 SRAM also supported
Fully Synchronous, Minimum Latency 30/33-MHz PCI Bus Interface
- Five PCI Bus Masters (including PIIX4)
- 10 DWord PCI-to-DRAM Read Prefetch Buffer
- 18 DWord PCI-DRAM Post Buffer
- Multi-Transaction Timer to Support
- Multiple Short PCI Transactions
Power Management Features
- PCI CLKRUN# Support
- Dynamic Stop Clock Support
- Suspend to RAM (STR)
- Suspend to Disk (STD)
- Power On Suspend (POS)
- Internal Clock Control
- SDRAM and EDO Self Refresh During Suspend
- ACPI Support
- Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM)
- SMM Writeback Cacheable in E_SMRAM Mode up to 1 MB
- 3.3/5V DRAM, 3.3/5V PCI 3.3/5V Tag and 3.3/2.5 SRAM Support
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