IBM PC/XT chipset
Chipset parts: Intel 8255A-5 (Programmable Peripheral Interface) Intel 8284A (Clock Generator and Driver) Intel 8288 (Bus Controller) Intel 8237A-5 (DMA Controller) Intel 8259A-2 (Programmable Interrupt Controller) Intel 8253-5 (Programmable Interval Timer) (any brand) Discrete Logic

Overview

The original chipsets used by IBM for the PC and XT are based on the Intel iAPX 88 system. Some additional components are taken from the MCS-80/85 system. The iAPX 88 system consists of the 8088 CPU and support chips. It is a modification of the iAPX 86 system (8086 CPU), with the iAPX 86 having a 16-bit external bus, and the iAPX 88 having an 8-bit external bus. The iAPX 86 system was formerly known as the MCS-86 system.

The chips used in the PC/XT were introduced by Intel at various different times between 1975 and 1981. In addition there are various different revisions of a particular chip. Due to these differences, relying on a datasheet from a particular year alone, may be insufficient. One thing that should be noted is the the A on the end of a part number is significant. If you click the encyclopedia link you can find a very detailed summary of the differences between the datasheets up to 1989. Using very early versions of chips manufactured before the introduction of the PC may cause unpredictable results.


Documented parts


Intel 8255A-5 Programmable Peripheral Interface

Versions:

  • 8255A Data Valid From READ: Max 250ns c78
  • 8255A-5 Data Valid From READ: Max 200ns c78 Compatible with PC/XT

Note, the 8255A is not the same as the 8255. The non-A is older, The A updated.

The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It has 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first mode (MODE 0), each group of 12 I/O pins may be programmed in sets of 4 to be input or output. In MODE 1, the second mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8 lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.

  • MCS-85 Compatible 8255A-5
  • 24 Programmable I/O Pins
  • Completely TTL Compatible
  • Fully Compatible with Intel Microprocessor Families
  • Improved Timing Characteristics
  • Direct Bit Set/Reset Capability Easing Control Application Interface
  • 40-Pin Dual In-Line Package
  • Reduces System Package Count
  • Improved DC Driving Capability

Intel 8284A Clock Generator and Driver

Versions

  • 8284A - 5-8MHz c:81
  • 8284A-1 - 10MHz c:82

Note, the 8284A is not the same as the 8284. The non-A is older, the A is updated.

The 8284A is a single chip clock generator/driver for the iAPX 86, 88 processors. The chip contains a crystal controlled oscillator, a divide-by-three counter, complete MULTIBUS "Ready" synchronization and reset logic.

  • Generates the System clock for the iAPX 86, 88 Processors [5 MHz, 8 MHz with 8284A 10 MHz with 8284A-1]
  • Uses a Crystal or a TTL Signal for Frequency Source
  • Provides Local READY and Multibus READY Synchronization
  • 18-Pin Package
  • Single +5V Power Supply
  • Generates System Reset Output from Schmitt Trigger Input
  • Capable of Clock Synchronization with Other 8284As

Intel 8288 Bus Controller

The Intel 8288 Bus Controller is a 20-pin bipolar component for use with medium-to-Large iAPX 86, 88 processing systems. The bus controller provides command and control timing generation as well as bipolar bus drive capability while optimizing system performance.

  • Bipolar Drive Capability
  • Provides Advanced Commands
  • Provides Wide Flexibility in System Configurations
  • 3-State Command Output Drivers
  • Configurable for Use with an I/O Bus
  • Facilitates Interface to One or Two Multi-Master Buses

Intel 8237A-5 DMA Controller

Versions:

  • 8237A - 3MHz
  • 8237A-4 - 4MHz
  • 8237A-5 - 5MHz (compatible with PC/XT/AT)

Note, the 8237A family is not the same as the 8237 family, which is older.

The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. Memory-to-memory transfer capability Is also provided. The 8237A offers a wide variety of programmable control features to enhance data throughput and system optimization and to allow dynamic reconfiguration under program control.

The 8237A Is designed to be used in conjunction with an external 8-bit address register such as the 8282. It contains four independent channels and may be expanded to any number of channels by cascading additional controller chips.

The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be individually programmed to Autoinitialize to its original condition following an End of Process (EOP).

Each channel has a full 64K address and word count capability.

The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected versions of the standard 3 MHz 8237A respectively.

  • Enable/Disable Control of Individual DMA Requests
  • Four Independent DMA Channels
  • Independent Autoinitialization of all Channels
  • Memory-to-Memory Transfers
  • Memory Block Initialization
  • Address Increment or Decrement
  • High Performance: Transfers up to 1.6M Bytes/Second with 5 MHz 8237A-2
  • Directly Expandable to any Number of Channels
  • End of Process Input for Terminating Transfers
  • Software DMA Requests
  • Independent Polarity Control for DREQ and DACK Signals

Intel 8259A-2 Programmable Interrupt Controller

mR_Slug notes:

Briefly the differences between the variants:

  • 8259A Data Valid From RD/INTA: Max 200ns c:79
  • 8259A-2 Data Valid From RD/INTA: Max 120ns c:81 compatible with PC/XT/AT
  • 8259A-8 Data Valid From RD/INTA: Max 300ns c:79

It's quickest to replace like with like. Note the non-A version has many more differences to the A versions. For a summary of differences see the following link, or consult the datasheets.

mR_Slug Intel Chip Specifications 1975 - 1989

Intel 8259A Programmable Interrupt Controller

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single +5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

  • 8086, 8088 Compatible
  • MCS-80, MCS-85 Compatible
  • Eight-Level Priority Controller
  • Expandable to 64 Levels
  • Programmable Interrupt Modes
  • Individual Request Mask Capability
  • Single + 5V Supply (No Clocks)
  • 28-Pin Dual-In-Line Package
  • Available in EXPRESS
    • Standard Temperature Range
    • Extended Temperature Range

Intel 8253 Programmable Interval Timer

The Intel 8253 is a programmable counter/timer chip designed for use as an Intel microcomputer peripheral. It uses nMOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.

It is organized as 3 independent 16-bit counters, each with a count rate of up to 2 MHz. All modes of operation are software programmable.

General

The 8253 is a programmable interval timer/counter specifically designed for use with the Intel Microcomputer systems. Its function is that of a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software.

The 8253 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in systems software, the programmer configures the 8253 to match his requirements, initializes one of the counters of the 8253 with the desired quantity, then upon command the 8253 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimal and that multiple delays can easily be maintained by assignment of priority levels.

Other counter/timer functions that are non-delay in nature but also common to most microcomputers can be implemented with the 8253.

  • Programmable Rate Generator
  • Event Counter
  • Binary Rate Multiplier
  • Real Time Clock
  • Digital One-Shot
  • Complex Motor Controller
  • MCS-85 Compatible 8253-5
  • 3 Independent 16-Bit Counters
  • DC to 2.6 MHz
  • Programmable Counter Modes
  • Count Binary or BCD
  • Single +5V Supply
  • 24 Pin Dual-in-line Package
  • Available in EXPRESS
    • Standard Temperature Range
    • Extended Temperature Range

Various Brands of Discrete Logic

A significant portion of this chipset is implemented in discrete logic. This typically refers to 7400 TTL DIP packages, but on more modern boards this may be surface-mount and/or include other family's. In this context it could include PALs, GALs, Gate Arrays and other chips that have either not been identified, or are not major chips.

Disclaimer

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